Various miniaturization technologies are being developed in order to increase the integration density of elements in a semiconductor device. Presently, by using such a miniaturization technology, transistor devices having a gate length of, for example, less than or equal to 90 nm, are being manufactured.
The purpose of increasing the integration density of elements in a semiconductor device includes increasing the driving speed and reducing power consumption. However, in a transistor device having a gate length of, for example, less than or equal to 90 nm, the leak current increases as the gate length decreases due to miniaturization. This impedes the reduction of power consumption. Meanwhile, when an attempt is made to reduce the leak current to less than or equal to a predetermined value, it becomes difficult to enhance the current driving capability of the transistor. As described above, there is a trade-off relationship between enhancing the driving capability of the transistor and reducing power consumption. Accordingly, new approaches are being sought to enhance the performance of transistors.
One of the new approaches is the strained silicon technology. This technology involves applying stress to a channel area and changing the energy band structure to reduce the effective mass of the carriers and to increase the carrier mobility, so that the current driving capability of the transistor is enhanced. It is known that in a metal-oxide semiconductor field-effect transistor (MOSFET), the carrier mobility is increased by applying uniaxial strain to the channel area. In a P-type channel transistor, hole mobility is increased by applying stress (compressive stress) for compressing the channel from the source/drain and generating compressive strain. In an N-type channel transistor, the mobility of electrons is increased by applying stress (tensile stress) for stretching the channel from the source/drain and generating tensile strain.
There is proposed a transistor having a so-called embedded structure. Specifically, to apply compressive stress or tensile stress to the channel area, a recess is formed in the source/drain area. In the recess, a material, which is different from that of the semiconductor substrate including the channel area, is epitaxially grown. For example, in a P-type channel transistor having a channel area of silicon (Si), silicon germanium (SiGe) is typically embedded as the source/drain area. Then, when the SiGe epitaxially grows, boron (B) is added by in-situ doping. Accordingly, the parasitic resistance of the source/drain is reduced. By reducing the resistance of the source/drain, the transistor performance is improved, in combination with the effect of increasing mobility by stress. In an N-type channel transistor having a Si channel area, carbon-doped silicon (SiC) is typically used instead of SiGe, and phosphorus (P) or arsenic (As) is typically used instead of B.
FIG. 1 schematically illustrates a transistor 10 having such an embedded structure. The transistor 10 includes a semiconductor substrate 11, a gate insulating film 21 formed on the semiconductor substrate 11, a gate electrode 22, and side walls 24. The transistor 10 includes source/drain areas 31 embedded in recesses formed in the semiconductor substrate 11. The transistor 10 further includes a pair of source/drain extension areas 33 provided below the side walls 24 and adjacent to the source/drain areas 31. Furthermore, a channel area 12 is positioned between the pair of source/drain extension areas 33, i.e., below the gate electrode 22. The source/drain extension areas 33 are formed by implanting ions after forming a pattern of the gate electrode 22. Subsequently, the side walls 24 are formed. Then, the source/drain areas 31 are formed by forming recesses and, causing selective epitaxial growth.
In the case of a P-type channel transistor, SiGe source/drain areas 31 in which B is doped at high density function as low resistance stressors that apply compressive stress to the channel area 12. However, in a short channel area, in order to prevent a short channel effect, the source/drain extension area is to be formed in a shallow, dense manner along the substrate direction. Accordingly, in conventional cases, such a source/drain extension area is typically formed by ion implantation. Meanwhile, there has been demand for applying strong compressive stress from the source/drain to the channel.
In order to respond to such demand, one approach is to reduce the source/drain extension areas 33 so that the SiGe source/drain areas 31 are closer to the channel area 12 and the stress applied to the channel area 12 is increased. However, making the SiGe source/drain areas 31 closer to the channel area 12 is the same as making the source/drain junction closer to the gate, as viewed in the distribution of B which is an impurity. Therefore, depletion layers from the source/drain interfere with each other due to B included in the SiGe source/drain areas 31. Consequently, a short channel effect occurs. Accordingly, the operations of the transistor cannot be controlled by the gate voltage. For this reason, there are limitations to make the SiGe source/drain areas 31 close to the channel area 12. Furthermore, when the density of B in the SiGe source/drain areas 31 is reduced for the purpose of improving roll-off properties, the parasitic resistance of the source/drain increases, and the speed of epitaxial growth decreases significantly, which are disadvantageous factors in terms of manufacturing products.
Another approach for preventing the stress from decreasing and for preventing the parasitic resistance from increasing due to the source/drain extension areas 33 is as follows. That is, the conventional source/drain extension areas 33 formed as a diffuse layer may be replaced by a layer formed as an epitaxial layer. FIG. 2 illustrates a transistor 100 including such an epitaxial layer. The transistor 100 may be substantially the same as the transistor 10 illustrated in FIG. 1, except that the source/drain extension areas 33 are replaced by epitaxial areas 132. The transistor 100 includes step-like source/drain epitaxial areas 130. The source/drain epitaxial areas 130 include first areas 131 corresponding to the conventional source/drain areas 31 and second areas that are the epitaxial areas 132 (shallower than the source/drain extension areas 33) provided adjacent to a channel area 112. For example, in a P-type transistor, the source/drain epitaxial areas 130 may be made of SiGe.
In the transistor 100, the source/drain epitaxial areas 130 (including the epitaxial areas (second areas) 132 adjacent to the channel area 112) function as a stressor. Therefore, stress is efficiently applied to the channel area 112, so that the hole mobility or electron mobility is increased. Furthermore, it is possible to reduce the parasitic resistance of the source/drain by doping B at high density in the source/drain epitaxial area 130 (including the shallow epitaxial areas (second areas) 132). Furthermore, a sufficient space is provided between the first areas 131 corresponding to the conventional source/drain areas 31 and the channel area 112, so that roll-off properties are prevented from degrading.
In order to form the transistor 100 including the step-like source/drain epitaxial area 130 indicated in FIG. 2, a process including a combination of forming a recess, embedding a stressor in the recess, and causing the stressor to grow, is to be typically performed twice. For example, after forming a gate electrode 122, recesses for the epitaxial areas (second areas) 132 are formed, and SiGe is caused to selectively grow in the recesses. Next, sidewalls 124 are formed. Then, recesses for the first areas 131 are formed, and SiGe is caused to selectively grow in the recesses. This method is complex and redundant compared to the method of manufacturing the transistor 10 described with reference to FIG. 1, because in this method, the process of forming the recesses and the process of selective epitaxial growth are to be respectively performed one more time, compared to the method of FIG. 1. Consequently, the manufacturing cost is increased.    Patent document 1: Japanese Laid-Open Patent Publication No. 2009-182109    Non-patent document 1: N. Yasutake and twelve others, “Record-high performance 32 nm node pMOSFET with advanced Two-step recessed SiGe-S/D and stress liner technology”, 2007 Symposium on VLSI Technology Digest of Technical Papers, 2007, pp. 48-49